Conventional semiconductor devices comprise a substrate and various electrically isolated regions, or so called active regions, in which individual circuit components are formed. Conventionally, the electrical isolation of these active regions is accomplished by the thermal oxidation of the semiconductor substrate, typically silicon, bounding the active regions. The conventional method for forming a field oxide comprises growing or depositing an oxide layer on the semiconductor substrate surface and depositing a nitride layer thereon. The oxide and nitride layers are patterned and etched employing conventional photolithography techniques to form a masking layer having openings extending down to and exposing the semiconductor substrate. The openings define areas on the surface of the semiconductor substrate in which field oxide regions are subsequently formed. These exposed regions are commonly referred to as the "field." The field oxide regions are formed by heating the semiconductor substrate with the field regions exposed to an oxidizing gas such as oxygen, i.e., a technique known as Local Oxidation of Silicon (LOCOS). Often, an ion implantation step is performed prior to the oxidation to ensure the proper functioning of the individually isolated circuit elements in the active regions.
Following the oxidation, the masking layers are removed by some combination of chemical and/or physical etching. A typical resulting prior art structure is shown in FIG. 1, wherein there is depicted a typical field oxide region 10 formed in the surface of a semiconductor substrate 1.
As can be observed in FIG. 1, either edge of the field oxide tapers in its vertical dimension both above and below the original surface of the semiconductor. This tapering end portion resembles and, therefore, is commonly referred to as, a "bird's beak." The bird's beak is formed during the thermal oxidation of the field regions because the oxygen which diffuses vertically into the substrate in the open areas also diffuses horizontally once it has penetrated the substrate. See, for example, Liu et al., U.S. Pat. No. 5,151,381 and Avanzino et al., U.S. Pat. No. 4,954,459.
This process has several inherent problems. For example, while the horizontal extent of the bird's beak can be loosely controlled by the stress induced in the masking layers adjacent to the field, this same stress can cause strain defects in the active areas including point defects, dislocations, stacking faults, as well as catastrophic failures such as delamination, particle generation, etc.
As shown in FIG. 1, the bird's beak region narrows the active region of the substrate between the field oxide regions in which active devices can be constructed down to a width X, with the width of the mask W minus X representing the area of lateral encroachment of the growth oxide. Typically, the degree of lateral encroachment of field oxide region 10 is no less than about ##EQU1## which normally corresponds to ##EQU2## To remedy this problem, the dimensions of the mask must be altered to accommodate encroachment, i.e., the openings for the field oxide region must be made smaller. However, reduction in the size of mask openings becomes a serious problem as the density of integrated circuit structures increases. Thus, as the dimensions of conductive lines and interwiring spaces are reduced into the submicron range, such as less than about 0.5 microns, even less than 0.25 microns, accuracy and, hence, manufacturability, are reduced. Further encroachment occurs upon lateral migration of the field implant, i.e., the doping beneath the field oxide, with the field oxide region during growth, thereby further reducing the active device region.
As disclosed in U.S. Pat. No. 4,954,459, the problems associated with growing a field oxide region in an integrated circuit have been recognized and addressed in different ways, such as utilizing a photoresist layer to etch a groove which is filled in with a deposited oxide before removing the photoresist mask. Another prior art technique reported in U.S. Pat. No. 4,954,459 comprises forming an isolation oxide by refilling anisotropically etched recesses in the silicon substrate with deposited oxide.
The inventive method disclosed in U.S. Pat. No. 4,954,459 comprises the use of a mechanically polishable planarization layer, such as a polysilicon layer, which is applied over an oxide layer and then polished down to the highest level of the oxide. The exposed oxide is then etched down to a predetermined level above the underlying integrated circuit structure after which the remaining polysilicon is removed by a further polishing step. The oxide may then be etched down to the level of the highest portions of the underlying integrated circuit structure.
Another type of isolation structure, distinct from a field oxide region, is known as trench isolation. A trench isolation structure is quite distinct from a field oxide region in that it is typically formed by etching a trench in the silicon substrate, normally about 0.30-0.50 microns deep, conducting a thermal oxidation step to grow an oxide layer on the trench walls to control the silicon-silicon dioxide interface quality, and refilling the trench with an insulator. The surface is then planarized to complete the trench isolation structure. Such a trench isolation structure disadvantageously requires complex processing steps and costly equipment.
In U.S. patent application Ser. No. 08/571,053 (filed on Dec. 12,1995), a technique is disclosed for forming a field dielectric region which avoids thermal oxidation. The disclosed method comprises introducing dielectric forming ions into the exposed portion of the semiconductor substrate, which dielectric forming ions combine with the substrate, typically silicon, to form a field dielectric region exhibiting a significantly reduced bird's beak and reduced bulging above the surface of the semiconductor substrate without thermal oxidation.
There are various types of semiconductor devices, such as electrically programmable semiconductor devices wherein a gate oxide is provided between the semiconductor substrate and a floating gate electrode. In such type semiconductor devices a section of the gate oxide typically exhibits a greater thickness in one section than in a different section, as in an adjoining section. For example, in FIG. 2 there is depicted a conventional prior art electrically erasable programmable read only memory (EEPROM) semiconductor device comprising substrate 20, source region 21, drain region 22, field oxide 23, gate oxide 24, floating gate 26, dielectric layer 28 and control gate 27. A portion of gate oxide layer 24 has a section of reduced thickness 25. It is difficult to form a gate oxide layer having sections with differential thicknesses.
There exists a need for a relatively simple, accurate, efficient and cost effective technique for forming a thermally oxidized field oxide region which, as formed, exhibits a substantially reduced bird's beak, thereby enabling the obtainment of minimal design features and spacings and, hence, high densification and integration. There also exists a need for a relatively simple, accurate, efficient and cost-effective technique for forming a gate oxide film having sections of different thicknesses.